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3.3GHz to 3.9GHz
Wireless Broadband RF Transceiver
Pin Description
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
NAME
VCCRXLNA
GNDRXLNA
B5
RXRF+
RXRF-
B4
VCCTXPAD
B3
B2
TXRF+
TXRF-
B1
PABIAS
VCCTXMX
CS
SCLK
CLKOUT
VCCDIG
REFCLK
VCCCP
GNDCP
CPOUT+
CPOUT-
GNDVCO
VCOBYP
VCCVCO
VCCLO
EXTVCO-
EXTVCO+
DOUT
DIN
RSSI
B7
B6
RXBBQ-
RXBBQ+
RXBBI-
RXBBI+
VCCRXVGA
FUNCTION
LNA Supply Voltage. Bypass with a capacitor as close as possible to the pin.
LNA Ground
Receiver and Transmitter Gain-Control Logic Input Bit 5
LNA Differential Inputs. Inputs are internally DC-coupled. Two external series capacitors and one
shunt inductor match the inputs to 100 Ω differential.
Receiver and Transmitter Gain-Control Logic Input Bit 4
Supply Voltage for Power-Amplifier Driver. Bypass with a capacitor as close as possible to the pin.
Receiver and Transmitter Gain-Control Logic Input Bit 3
Receiver and Transmitter Gain-Control Logic Input Bit 2
Power-Amplifier Driver Differential Output. Outputs are internally DC-coupled. Two external series
capacitors and one shunt inductor match the outputs to 100 Ω differential.
Receiver and Transmitter Gain-Control Logic Input Bit 1
Transmit PA Bias DAC Output
Transmitter Upconverter Supply Voltage. Bypass with a capacitor as close as possible to the pin.
Chip-Select Logic Input of 4-Wire Serial Interface (See Figure 1)
Serial-Clock Logic Input of 4-Wire Serial Interface (See Figure 1)
Reference Clock Divided Output
Digital Circuit Supply Voltage. Bypass with a capacitor as close as possible to the pin.
Reference Clock Input
PLL Charge-Pump Supply Voltage. Bypass with a capacitor as close as possible to the pin.
Charge-Pump Circuit Ground
Differential Charge-Pump Output. Connect the frequency synthesizer’s loop filter between CPOUT+
and CPOUT- (see the Typical Operating Circuit ).
VCO Ground
On-Chip VCO Regulator Output Bypass. Bypass with a 1μF capacitor to GND. Do not connect other
circuitry to this point.
VCO Supply Voltage. Bypass with a capacitor as close as possible to the pin.
LO Generation Supply Voltage. Bypass with a capacitor as close as possible to the pin.
External VCO Differential Input or Output. Input for slave configuration and output for master
configuration. Leave unconnected for single configuration.
Data Logic Output of 4-Wire Serial Interface (See Figure 1)
Data Logic Input of 4-Wire Serial Interface (See Figure 1)
RSSI or Temperature Sensor Multiplexed Analog Output
Receiver Gain-Control Logic Input Bit 7
Receiver and Transmitter Gain-Control Logic Input Bit 6
Receiver Baseband Q-Channel Differential Outputs. In Tx calibration mode, these pins are the LO
leakage and sideband detector outputs.
Receiver Baseband I-Channel Differential Outputs. In Tx calibration mode, these pins are the LO
leakage and sideband detector outputs.
Receiver VGA Supply Voltage. Bypass with a capacitor as close as possible to the pin.
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17
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